Field of the Invention
The present invention relates to memory systems having a memory controller in communication with a plurality of memory modules.
Background of the Related Art
A fundamental hardware component of a computer is the memory that is used to store information for high speed access by a central processing unit. The memory is typically an addressable volatile or non-volatile integrated circuit. One example of a memory device is a dual in-line memory module (DIMM) supporting a series of dynamic random-access memory chips and having an edge connector that is received into a slot on a motherboard.
The central processing unit communicates with the memory through a memory controller. The memory controller establishes a memory interface or memory bus that includes a number of parallel data lanes extending between the memory controller and each of the memory modules. In some instances, the memory interface may include 64 data lanes in order to transfer 64 bits of data at a time. The number of data lanes, as well as the memory bus clock rate and whether the interface uses single data rate (SDR) or double data rate (DDR), contributes to the bandwidth of the memory interface.
With today's high speed memory interfaces, the memory controller must train each data channel for each DIMM in a system. This training process optimizes the performance of the data lanes, but takes most of the time in a system boot. In some cases, the DIMM training process gets fairly far along before a bad data lane is detected.